JPS633159Y2 - - Google Patents
Info
- Publication number
- JPS633159Y2 JPS633159Y2 JP1980054470U JP5447080U JPS633159Y2 JP S633159 Y2 JPS633159 Y2 JP S633159Y2 JP 1980054470 U JP1980054470 U JP 1980054470U JP 5447080 U JP5447080 U JP 5447080U JP S633159 Y2 JPS633159 Y2 JP S633159Y2
- Authority
- JP
- Japan
- Prior art keywords
- case
- connection terminals
- connection
- terminals
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980054470U JPS633159Y2 (en]) | 1980-04-23 | 1980-04-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980054470U JPS633159Y2 (en]) | 1980-04-23 | 1980-04-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56157758U JPS56157758U (en]) | 1981-11-25 |
JPS633159Y2 true JPS633159Y2 (en]) | 1988-01-26 |
Family
ID=29649215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1980054470U Expired JPS633159Y2 (en]) | 1980-04-23 | 1980-04-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS633159Y2 (en]) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3795845A (en) * | 1972-12-26 | 1974-03-05 | Ibm | Semiconductor chip having connecting pads arranged in a non-orthogonal array |
-
1980
- 1980-04-23 JP JP1980054470U patent/JPS633159Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS56157758U (en]) | 1981-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5151771A (en) | High lead count circuit board for connecting electronic components to an external circuit | |
US5726860A (en) | Method and apparatus to reduce cavity size and the bondwire length in three tier PGA packages by interdigitating the VCC/VSS | |
JPS633159Y2 (en]) | ||
JPH06291230A (ja) | 複合半導体装置の製造方法 | |
JP3295457B2 (ja) | 半導体装置 | |
JPS6032778Y2 (ja) | リ−ドレスチツプキヤリヤ | |
JPH0770666B2 (ja) | 集積回路装置実装パツケ−ジ | |
JP2596399B2 (ja) | 半導体装置 | |
JPS58153432U (ja) | 放電ギヤツプ付cr複合部品 | |
JPS642440Y2 (en]) | ||
JPS6120780Y2 (en]) | ||
JPS5862532U (ja) | 温度ヒユ−ズ | |
JPS62123744A (ja) | 半導体装置 | |
JP2752932B2 (ja) | 半導体集積回路パッケージ | |
JPS5895860A (ja) | 多層構造半導体装置 | |
JPS5890639U (ja) | 温度ヒユ−ズ | |
JPS63169746A (ja) | 半導体装置 | |
JPS60202958A (ja) | 混成集積回路装置 | |
KR920001699A (ko) | 반도체장치 | |
JPS611213U (ja) | 平型絶縁電線 | |
JPH0268452U (en]) | ||
JPS6169847U (en]) | ||
JPS60194315U (ja) | インダクタンス素子 | |
JPS60872U (ja) | ア−スリ−ド線付き気密端子 | |
KR19990003760U (ko) | 반도체 패키지 및 인쇄회로기판과의 결합구조 |